SPICE OPUS

SPICE OPUS is a free general purpose electronic circuit simulator, developed and maintained by members of EDA Group, University of Ljubljana, Slovenia. It is based on original Berkeley’s SPICE analog circuit simulator and includes various improvements and advances, such as memory-leak bug fixes and plotting tool improvements. SPICE OPUS is specially designed for fast optimization loops via its built-in optimizer.

SPICE OPUS analyses and processing is done using NUTMEG interpreted programming language, which allows interactive SPICE OPUS sessions. SPICE OPUS can also be used as a batch simulator that stores its results in output files (ASCII and binary RAW file format is supported).

SPICE OPUS started in the mid-1990s as a teaching and research tool for circuit design and optimization at the Faculty of Electrical Engineering, University of Ljubljana. At the time only Windows operating system was supported as this was the preferred choice of most students at that time. In 1999 a Linux version (1.0) was released with the help of the cross platform Qt library. XSPICE extensions were added in version 2.0. Several bugs were reported to be removed and features were added over the next decade. The latest addition (version 3.0) is the support of OpenVAF-compiled Verilog-A models via its OSDI interface.

Between years 2000 and 2023, SpiceOpus is reported to be used as a tool for teaching the theory of circuit simulation and algorithms in higher education in several universities.

Similarly, it has been widely used in academia for scientific research of systems, electronics and algorithms for EDA.

Available analyses

• Operating point (OP) Analysis
• Operating point Sweep Analysis (DC Analysis)
• DC Transfer Function Analysis (TF Analysis)
• Small Signal Analysis (AC Analysis)
• Pole-Zero (PZ) Analysis
• Noise (NOISE) Analysis
• Transient (TRAN) Analysis

SPICE OPUS comes with several device models

• basic circuit components like votage and current sources, resistors, capacitors, bipolar transistors, diodes, ...
• advanced models like BSIM3, BSIM3SOI, BSIM4, SOI3, UFS, UFET, EKV, ...
• XSPICE code models for behavioral modeling and event-driven simulation
• special code models for small-signal modelling in frequency domain: ZARC and constant phase element (CPE).
• a library of compact models written in Verliog-A (BSIMBULK, BSIMCMG, HICUM, EKV, HiSIM, MEXTRAM, ...)

Following approaches for adding user-defined models are supported:

• Behavioral voltage and current sources (B devices)
• XSPICE code models written in C
• Verilog-A models that can be compiled with OpenVAF compiler

SPICE OPUS supports parameterized netlists, parameterized subcircuits, and topology changes without simulator restart (netclass).

As a supported simulator in PyOPUS optimization library SPICE OPUS can be used as a simulation engine for advanced circuit analyses (Monte Carlo, sensitivity, worst-case, worst-case distance) and automated design procedures (nominal design, corner-based design, yield targeting).

Schematic entry is available via an interface to the KiCAD schematic editor in the PyOPUS library or Qucs-S: Qucs circuit simulation software package. Usage of SpiceOpus is also reported in web-application for circuit schematics editing GEEC