| Architecture Overview | |
|---|---|
| Developer | AMD / Intel / TSMC |
| Released | 2024–present |
| Market segment | High-Performance Computing (HPC), Data Center |
| Die Configuration | |
| Total chiplets | Multi-die (variable configuration) |
| Compute dies | CPU / GPU Core Tiles |
| I/O dies | Centralized Base I/O Die |
| Memory dies | HBM3 / 3D V-Cache Stacks |
| Packaging & Interconnect | |
| Packaging tech | 2.5D Organic Substrate / 3D Stacking |
| Interconnect protocol | UCIe / Proprietary Fabric |
| Bump pitch | 25 μm to 130 μm |
| Process Nodes | |
| Compute node | 3 nm / 5 nm |
| I/O node | 6 nm / 14 nm |
| Foundry | TSMC / Intel Foundry Services |
A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package to create a complex component such as a computer processor. Each chiplet in a computer processor provides only a portion of the processor's total functionality. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC) which is monolithic as it comprises a single silicon die:
While chiplets offer significant advantages in yield and cost, they also introduce new thermal management challenges. Because multiple dies are packed closely together on a single package, the power density can be extremely high, requiring advanced cooling solutions. Furthermore, ensuring reliable high-bandwidth communication between dies from different manufacturers remains an engineering hurdle, which is being addressed by interconnect standards like UCIe and BoW.
Multiple chiplets working together in a single integrated circuit may be called a multi-chip module, hybrid IC, 2.5D IC, or advanced package.
Chiplets may be connected with standards such as UCIe, bunch of wires (BoW), AIB (Advanced Interface Bus), OpenHBI (Open High Bandwidth Interface), and OIF (Optical Internetworking Forum) XSR (Extra Short Reach). Chiplets not designed by the same company must be designed with interoperability in mind.
The term was coined by University of California, Berkeley professor John Wawrzynek as a component of the RAMP Project (research accelerator for multiple processors) in 2006 extension for the Department of Energy.
Common examples include: