Fe FET

A ferroelectric field-effect transistor (Fe FET) is a type of field-effect transistor that includes a ferroelectric material sandwiched between the gate electrode and source–drain conduction region of the device (the channel). Permanent electrical field polarisation in the ferroelectric causes this type of device to retain the transistor's state (on or off) in the absence of any electrical bias.

FeFET based devices are used in FeFET memory – a type of single-transistor non-volatile memory and also in artficial neuron circuits .

Description

In 1955, Ian Munro Ross filed a patent for a FeFET, or MFSFET. Its structure was like that of a modern inversion-channel MOSFET, but ferroelectric material was used as a dielectric/insulator instead of oxide. Use of a ferroelectric (triglycine sulfate) in a solid-state memory was proposed by Moll and Tarui in 1963 using a thin-film transistor. Further research occurred in the 1960s, but the retention characteristics of the thin-film-based devices was unsatisfactory. Early devices based on field-effect transistors used bismuth titanate (Bi
4Ti
3O
12) ferroelectric, or Pb
1−xLn
xTiO
3 (PLT) and related mixed zirconate/titanates (PLZT). In the late 1980s, ferroelectric RAM was developed, using a ferroelectric thin film as capacitor, connected to an addressing FET.

FeFET-based memory devices are read using voltages below the coercive voltage for the ferroelectric.

Issues involved in realising a practical FeFET memory device include (as of 2006): choice of a high-permitivity, highly insulating layer between ferroelectric and gate; issues with high remanent polarisation of ferroelectrics; limited retention time (only a few days instead of required 10 years).

Provided that the ferroelectric layer can be scaled accordingly, FeFET-based memory devices are expected to scale (shrink) as well as MOSFET devices; however a limit of ~20 nm laterally may exist (the superparaelectric limit, aka ferroelectric limit). Other challenges to feature shrinks include: reduced film thickness causing additional (undesired) polarisation effects; charge injection; and leakage currents.

Research and development

Structure of a 1-transistor FeFET cell

In 2017, FeFET based non-volatile memory was reported as having been built at 22 nm node using FDSOI CMOS (fully depleted silicon on insulator) with hafnium dioxide (HfO
2) as the ferroelectric. The smallest FeFET cell size reported was 0.025 μm2. The devices were built as 32 Mbit arrays, using set/reset pulses of ~10 ns duration at 4.2 V. The devices showed endurance of 105 cycles and data retention up to 300 °C.

As of 2017, the startup Ferroelectric Memory Company is attempting to develop FeFET memory into a commercial device, based on hafnium dioxide. The company's technology is claimed to scale to modern process node sizes and to integrate with contemporary production processes, i.e. HKMG, and is easily integrable into conventional CMOS processes, requiring only two additional masks.

See also

References

  1. ↑ Wang, Dong; Hao, Shenglan; Dkhil, Brahim; Tian, Bobo; Duan, Chungang (2024-09-01). "Ferroelectric materials for neuroinspired computing applications". Fundamental Research. 4 (5): 1272–1291. doi:10.1016/j.fmre.2023.04.013. PMC 11489484. PMID 39431127.
  2. ↑ Stefan Ferdinand Müller (2016). Development of HfO2-Based Ferroelectric Memories for Future CMOS Technology Nodes. BoD – Books on Demand. ISBN 978-3-7392-4894-3.
  3. ↑ Park et al. 2016, §1.1.1, p. 3.
  4. 1 2 3 Park et al. 2016, §1.1.1, p. 4.
  5. ↑ Park et al. 2016, §1.1.2, p. 6.
  6. 1 2 Waser, R. (2005), "Scaling of Ferroelectric-Based Memory Concepts §Ferrorelectric Field-Effect Transistors (FeFET)", in Zschech, Ehrenfried; Whelan, Caroline; Mikolajick, Thomas (eds.), Materials for Information Technology: Devices, Interconnects and Packaging, Springer, pp. 157–9, ISBN 978-1-84628-235-5
  7. ↑ Khosla, Robin; Sharma, Deepak K.; Mondal, Kunal; Sharma, Satinder K. (2014-10-13). "Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors". Applied Physics Letters. 105 (15): 152907. Bibcode:2014ApPhL.105o2907K. doi:10.1063/1.4897952. ISSN 0003-6951.
  8. ↑ Dünkel, S. (December 2017), "A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond", 2017 IEEE International Electron Devices Meeting (IEDM), pp. 19.7.1–4, doi:10.1109/IEDM.2017.8268425, ISBN 978-1-5386-3559-9, S2CID 19624615
  9. ↑ Lapedus, Mark (16 Feb 2017). "What Are FeFETs?". Semiconductor Engineering.

Further reading