In computer science, load-linked/store-conditional (LL/SC), sometimes known as load-reserved/store-conditional (LR/SC), are a pair of instructions used in multithreading to achieve synchronization. Load-link returns the current value of a memory location, while a subsequent store-conditional to the same memory location will store a new value only if no updates have occurred to that location since the load-link. Together, this implements a lock-free, atomic, read–modify–write operation.
"Load-linked" is also known as load-link, load-reserved, and load-locked.[citation needed]
If any updates have occurred, the store-conditional is guaranteed to fail, even if the value read by the load-link has since been restored. As such, an LL/SC pair is stronger than a read followed by a compare-and-swap (CAS), which will not detect updates if the old value has been restored (see ABA problem).
Real implementations of LL/SC do not always succeed even if there are no concurrent updates to the memory location in question. Any exceptional events between the two operations, such as a context switch, another load-link, or even (on many platforms) another load or store operation, will cause the store-conditional to spuriously fail. Older implementations will fail if there are any updates broadcast over the memory bus. This is called weak LL/SC by researchers, as it breaks many theoretical LL/SC algorithms. Weakness is relative, and some weak implementations can be used for some algorithms.
LL/SC is more difficult to emulate than CAS. Additionally, stopping running code between paired LL/SC instructions, such as when single-stepping through code, can prevent forward progress, making debugging tricky.
Nevertheless, LL/SC is equivalent to CAS in the sense that either primitive can be implemented in terms of the other, in O(1) and in a wait-free manner.
Some CPUs[which?] require the address being accessed exclusively to be configured in write-through mode.
All of these platforms provide weak[clarification needed] LL/SC. The PowerPC implementation allows an LL/SC pair to wrap loads and even stores to other cache lines (although this approach is vulnerable to false cache line sharing). This allows it to implement, for example, lock-free reference counting in the face of changing object graphs with arbitrary counter reuse (which otherwise requires double compare-and-swap, DCAS). RISC-V provides an architectural guarantee of eventual progress for LL/SC sequences of limited length.
Typically, CPUs track the load-linked address at a cache-line granularity, such that the store-conditional will only succeed if the cache line has been an exclusive (to this processor) cache state continuously since the linked load. Any other processor must demote it from this state before a write (store-conditional or an ordinary store) may complete.
Some ARM implementations define platform dependent blocks, ranging from 8 bytes to 2048 bytes, and an LL/SC attempt in any given block fails if there is between the LL and SC a normal memory access inside the same block. Other ARM implementations fail if there is a modification anywhere in the whole address space. The former implementation is the stronger and most practical.
LL/SC fits naturally into a load–store architecture, as reads and writes are separate instructions which can use the standard instruction pipeline. Also, both instructions can be performed using only two registers (address and value), fitting naturally into common 2-operand ISAs. The most significant complication is the need to report a boolean success indication from the store. CAS, on the other hand, requires three registers (address, old value, new value) and a dependency between the value read and the value written. x86, for example, only allows the address and new value to be located arbitrarily; the old value must be in the EAX register. Modern chips, which translate complex instructions into internal micro-operations, may well translate a CAS instruction into separate LL/SC micro-operations.
Extensions
Hardware LL/SC implementations typically do not allow nesting of LL/SC pairs. A nesting LL/SC mechanism can be used to provide a MCAS primitive (multi-word CAS, where the words can be scattered). In 2013, Trevor Brown, Faith Ellen, and Eric Ruppert implemented in software a multi-address LL/SC extension (which they call LLX/SCX) that relies on automated code generation; they have used it to implement one of the best-performing concurrent binary search tree (actually a chromatic tree), slightly beating the JDK CAS-based skip list implementation.
↑James H. Anderson; Mark Moir (1995). "Universal constructions for multi-object operations". PODC '95 Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing. ACM. pp.184–193. doi:10.1145/224964.224985. ISBN0-89791-710-3. S2CID8204331. See their Table 1, Figures 1 & 2 and Section 2 in particular.
↑May, Cathy; Silha, Ed; Simpson, Eick; Warren, Hank (1993). The PowerPC architecture: A SPECIFICATION FOR A NEW FAMILY OF RISC PROCESSORS. Morgan Kaufmann PUblishers, Inc. pp.336–338, 465. ISBN1-55860-316-6.
Bruner, John D.; Hagensen, Gary W.; Jensen, Eric H.; Pattin, Jay C.; Broughton, Jeffrey M. (11 November 1987). Cache Coherence on the S-1 AAP(PDF) (Technical report). Lawrence Livermore National Laboratory. UCRL-97646. Archived from the original(PDF) on 2 February 2017. Retrieved 10 November 2013.
Detlefs, D.; Martin, P.; Moir, M.; Steele, Jr., Guy L. (2001). "Lock-free reference counting". PODC '01 Proceedings of the twentieth annual ACM symposium on Principles of distributed computing. ACM. pp.190–9. CiteSeerX10.1.1.92.8221. doi:10.1145/383962.384016. ISBN1-58113-383-9. {{cite book}}: Cite uses deprecated parameter |citeseerx= (help)
