Scientific Research Institute of System Development

Microprocessors

The SRISA has designed several MIPS compatible CPUs for general purpose calculations. These include:

• KOMDIV-32 (Russian: КОМДИВ-32) is a family of 32-bit microprocessors, MIPS-I ISA
• KOMDIV-64 (Russian: КОМДИВ-64) is a family of 64-bit microprocessors, MIPS-IV ISA
• KOMDIV-64 (Russian: КОМДИВ-64) is a family of 64-bit microprocessors, MIPS-IV ISA
• "1890VM8Ya" is a 64-bit microprocessors, used in the CPU module on "TSP16/TSP21", integrated computer system at Sukhoi Su-57 "fifth-generation jet fighter" and Su-35 "4++ generation jet fighter".

Dual-core 64-bit superscalar microprocessor with KOMDIV64 architecture with integrated system and peripheral controllers, second-level cache memory and additional functions for digital signal processing. Main characteristics:

• support for 32-bit instruction execution mode and addressing mode;
• the presence of a real arithmetic coprocessor that supports the formats for representing real numbers of single (32 bits) and double (64 bits) precision, as well as the format "pair of real numbers of single precision";
• the presence of a specialized vector coprocessor optimized for linear algebra and digital signal processing tasks of single and double precision with a separate register file of 64 128-bit registers, supporting single and double precision real and complex number formats;
• translation of 32-bit and 64-bit virtual addresses into 36-bit physical ones;
• 64-address (128-page) virtual translation lookaside buffer (jTLB);
• separate virtual address translation buffer (micro TLB) caches for 4 addresses for instructions and data, transparent to the software model;
• separate set-associative first-level instruction caches of 32 KB (8 sections) and data of 16 KB (4 sections);
• 2-level cache memory of 512 KB (4 sections);
• 128-bit internal bus;
• 7-stage superscalar pipeline with instruction prefetching and the ability to execute two instructions per cycle;
• reading up to four commands per clock cycle;
• dynamic branch prediction and speculative instruction execution.
• 2 DDR2/DDR3 400/800 MHz dynamic memory controllers;
• 2 RapidIO interface controllers;
• built-in RapidIO switch with 4 serial and one parallel channels;
• PCI controller 33/66 MHz;
• RS232 serial port controller (2 ports);
• 2 Ethernet 1000/100/10 controllers;
• 1 SATA 3.0 controller with 2 channels;
• 1 USB 2.0 host controller with 2 channels;
• SPI controller (4 devices);
• I2C controller;
• 16 one-time commands;
• interrupt controller;
• 5 timers;
• EJTAG in-circuit debugging controller.

Operating systems

Since 1998 the SRISA department of System Programming has develop several successive UNIX-like real-time operating system (RTOS) that include:

• POSIX 1003.1-compatible RTOS developed since January 1998; the network sockets, however, were borrowed from Free BSD; it supported TCP/IP protocol and X Window suite; it runs on MIPS based CPUs mentioned above.
• POSIX 1003.1 and Arinc 653-compatible RTOS was first exhibited at SofTool-2008, -2009, and -2010 in Moscow. It was joint project between Alt Linux and SRISA teams.^: 70