List of free and open-source EDA software

KiCad V6 PCB view of the open-source project Glasgow

This is a list of free and open-source EDA software, including software used for electronic design automation (EDA) in integrated circuit (IC), field-programmable gate array (FPGA), printed circuit board (PCB), and electronic-system design. EDA software is used for tasks including schematic capture, circuit simulation, hardware description language processing, logic synthesis, functional verification, static timing analysis, place and route, physical verification, and IC and PCB layout.

Many free and open-source EDA tools are designed for a particular stage of the design process and are combined into larger toolchains. For example, OpenROAD Flow Scripts integrates Yosys, OpenROAD, and KLayout into an automated RTL-to-GDSII digital IC design flow.

Integrated design flows and frameworks

Name Target License Description
Hammer ASIC BSD-3-Clause Technology-agnostic physical-design framework developed by UC Berkeley for constructing reusable ASIC design flows and interfacing with different EDA tools and process technologies.
OpenFASoC Analog and mixed-signal SoC Apache-2.0 Automated analog and mixed-signal circuit-generation framework that generates physical designs from user specifications using open-source EDA tools.
OpenLane ASIC Apache-2.0 Automated RTL-to-GDSII ASIC implementation infrastructure using tools including Yosys, OpenROAD, Magic, Netgen, and KLayout.
OpenROAD Flow Scripts ASIC BSD-3-Clause Automated RTL-to-GDSII reference flow integrating Yosys for synthesis, OpenROAD for physical implementation, and KLayout for final layout processing and verification.
OSS CAD Suite Digital logic and FPGA Various Binary distribution of open-source tools for RTL synthesis, formal verification, simulation, FPGA place and route, programming, and related digital-design tasks.
SiliconCompiler ASIC and FPGA Apache-2.0 Modular hardware build system that orchestrates open-source and proprietary EDA tools for synthesis, simulation, physical design, and verification.

Hardware description and construction languages

Name Base language Output License Description
Amaranth Python Verilog BSD-2-Clause Hardware-definition language and toolchain for describing synchronous digital logic, simulation, and FPGA or ASIC development.
Chisel Scala SystemVerilog Apache-2.0 Hardware construction language for creating parameterized digital circuits and reusable hardware generators for ASIC and FPGA designs.
Clash Haskell VHDL, Verilog, SystemVerilog BSD-2-Clause Functional hardware description language and compiler based on Haskell that generates synthesizable HDL for digital circuits.
MyHDL Python Verilog, VHDL LGPL-2.1 Python-based hardware description and verification language supporting simulation and conversion to synthesizable Verilog and VHDL.
PyRTL Python Verilog BSD-3-Clause Python library for register-transfer level hardware design, simulation, testing, synthesis, and Verilog generation.
SpinalHDL Scala VHDL, Verilog, SystemVerilog LGPL-3.0 and MIT Hardware description language and associated tools for generating RTL designs using Scala, with output compatible with standard EDA toolchains.

Hardware compiler and HDL development tools

Name Target License Description
CIRCT Hardware compiler infrastructure Apache-2.0 with LLVM exceptions LLVM incubator project applying MLIR compiler infrastructure to hardware design, including intermediate representations and transformation tools for digital hardware.
slang SystemVerilog MIT SystemVerilog compiler and language-services library providing parsing, type checking, linting, abstract syntax trees, and Python bindings.
Surelog SystemVerilog Apache-2.0 SystemVerilog preprocessor, parser, elaborator, and compiler that produces the Universal Hardware Data Model for use by synthesis, simulation, and verification tools.
Verible SystemVerilog Apache-2.0 Suite of SystemVerilog development tools including a parser, formatter, style linter, and language server.

High-level synthesis and logic synthesis

Name Target License Description
Bambu ASIC and FPGA GPL-3.0 High-level synthesis tool in the PandA framework that synthesizes hardware accelerators from C and C++ descriptions.
Yosys ASIC and FPGA ISC Framework for RTL synthesis with extensive Verilog support and support for synthesizable SystemVerilog.

Simulation and verification

Name Target License Description
cocotb Functional verification BSD-3-Clause Python-based coroutine and cosimulation framework for writing hardware testbenches that interact with HDL simulators through interfaces including VPI and VHPI.
gem5 Computer architecture BSD 3-Clause Modular computer-system architecture simulator for system-level architecture and processor microarchitecture research.
GHDL VHDL GPL-2.0-or-later VHDL analyzer, compiler, simulator, and experimental synthesis tool supporting multiple revisions of the VHDL standard.
Icarus Verilog Verilog and SystemVerilog GPL-2.0-or-later Verilog compilation and simulation system supporting preprocessing, elaboration, optimization, simulation, and multiple code-generation targets.
SymbiYosys Formal verification ISC Front-end for Yosys-based formal hardware verification flows using techniques including bounded model checking and proof engines.
Verilator Verilog and SystemVerilog LGPL-3.0-only or Artistic-2.0 Compiles synthesizable Verilog and SystemVerilog into cycle-accurate C++ or SystemC models for simulation and verification.

Waveform viewers

Name Target License Description
GTKWave Digital waveforms GPL-2.0-or-later Waveform viewer supporting formats including VCD, FST, and GHW for examining signals produced by HDL simulators.

Memory compilers and generators

Name Target License Description
OpenCache Cache BSD-3-Clause Custom cache generator that creates synthesizable Verilog cache logic and uses OpenRAM-generated SRAM arrays.
OpenRAM SRAM BSD-3-Clause Memory compiler that generates SRAM layouts, netlists, timing and power models, placement-and-routing models, and other views for ASIC design.
OpenROM ROM BSD-3-Clause ROM compiler included with OpenRAM that generates physical ROM designs from binary or hexadecimal data.
OpenTCAM TCAM Apache-2.0 Configurable SRAM-based TCAM compiler capable of generating RTL for FPGA designs and GDSII layouts for ASIC designs using OpenRAM-generated SRAMs.

FPGA implementation

Name Target License Description
nextpnr FPGA ISC Vendor-neutral, timing-driven FPGA place-and-route tool supporting multiple FPGA architectures and open bitstream projects.
Verilog-to-Routing FPGA MIT and other permissive licenses FPGA CAD and architecture-research framework incorporating synthesis, logic optimization, packing, placement, routing, and timing analysis, including the VPR place-and-route tool.

Physical design and timing analysis

Name Target License Description
iEDA ASIC MulanPSL-2.0 Open-source physical-design infrastructure and toolchain for implementing ASIC netlists through placement, clock-tree synthesis, routing, timing analysis, and GDS generation.
OpenROAD ASIC BSD-3-Clause Physical-design application providing stages including floorplanning, placement, clock tree synthesis, routing, and optimization for automated RTL-to-GDSII flows.
OpenSTA Static timing analysis GPL-3.0 Static timing analysis engine supporting industry-standard formats including Liberty, Verilog, SDC, SPEF, and SDF.
OpenTimer Static timing analysis MIT Parallel and incremental static timing analyzer supporting Liberty, Verilog, SPEF, and SDC design data.

Layout generation and geometry libraries

Name Target License Description
GDSFactory IC, photonic, analog, quantum, and MEMS layout MIT Python-based chip-design framework for generating parametric layouts, routing, simulation interfaces, process design kits, and verification workflows, with output including GDSII and OASIS files.
Gdstk GDSII and OASIS layout BSL-1.0 C++ and Python library for creating and manipulating GDSII and OASIS layouts, including polygon operations, offsets, paths, and hierarchical cells.
KFactory IC and photonic layout MIT Python layout framework built on the KLayout geometry engine, providing parametric cells, electrical and optical routing, PDK support, netlist extraction, and layout-versus-schematic verification.
PHIDL GDSII layout MIT Python-based CAD library for creating parameterized GDS layouts, including geometric operations, routing, device ports, and structures for photonic and nanofabrication designs.

IC layout and physical verification

Name Target License Description
Electric IC layout and schematic design GPL-3.0-or-later Integrated-circuit design system supporting schematic capture, custom IC layout, design-rule checking, layout-versus-schematic verification, simulation, placement, and routing.
KLayout IC layout and physical verification GPL-2.0-or-later IC layout editor and viewer with scripting and automation facilities used for viewing and manipulating GDSII and other layout formats and for design-rule and layout-versus-schematic verification.
Magic VLSI layout BSD VLSI layout editor providing layout creation, extraction, routing, and design-rule checking and used by open-source ASIC design flows.
Netgen LVS GPL Netlist comparison and management tool primarily used for layout-versus-schematic verification of SPICE and Verilog netlists.

Semiconductor device simulation

Name Target License Description
DEVSIM TCAD Apache-2.0 Semiconductor-device simulator using finite-volume methods for solving electrical and other partial differential equations on one-, two-, and three-dimensional device structures.

Analog and mixed-signal design

Name Target License Description
Ngspice Analog and mixed-signal simulation Modified BSD and compatible licenses Mixed-level and mixed-signal circuit simulator derived from SPICE3, Cider, and XSPICE and commonly used for SPICE-based circuit simulation.
Oregano Schematic capture and circuit simulation GPL-2.0 Graphical schematic-capture application that performs circuit simulation using engines including Ngspice and Gnucap.
Qucs-S Circuit simulation GPL-2.0 Graphical schematic capture and circuit-simulation frontend supporting simulation engines including Ngspice and Xyce.
XCircuit Schematic capture GPL-2.0 Schematic-capture and circuit-drawing application for creating electronic circuit diagrams and generating circuit netlists.
Xschem Schematic capture GPL-2.0-or-later Schematic editor for VLSI, ASIC, and analog circuit design with netlist generation for SPICE, VHDL, and Verilog.
Xyce Analog circuit simulation GPL-3.0-or-later SPICE-compatible parallel electronic circuit simulator developed at Sandia National Laboratories for simulation ranging from desktop systems to large parallel computers.

Printed circuit board design

Name Target License Description
Fritzing PCB GPL-3.0 Electronics design application providing breadboard, schematic, and PCB views and tools for creating PCB layouts.
Horizon EDA PCB GPL-3.0 Integrated PCB design application providing schematic capture, parts and library management, PCB layout, design-rule checking, and manufacturing-output generation.
KiCad PCB GPL-3.0 EDA suite providing schematic capture, PCB layout, circuit simulation, component-library management, and manufacturing-output generation.
LibrePCB PCB GPL-3.0 Cross-platform EDA suite for schematic capture and printed circuit board design.
pcb-rnd PCB GPL-2.0-or-later Modular printed circuit board layout editor descended from the PCB program associated with the gEDA project.

Electromagnetic and signal-integrity simulation

Name Target License Description
gerber2ems PCB signal integrity Apache-2.0 Python interface that converts PCB manufacturing data into openEMS simulations for analyzing printed-circuit-board traces and signal integrity.
openEMS Electromagnetic simulation GPL-3.0 Three-dimensional electromagnetic field solver using the finite-difference time-domain method for applications including RF and microwave circuits, antennas, and electromagnetic-wave propagation.

See also

Open-source processor hardware

Instruction sets

Projects and organizations

Processor cores and SoCs

References

  1. ↑ "Glasgow Interface Explorer". GitHub. GlasgowEmbedded. Retrieved September 18, 2026.
  2. ↑ Baungarten-Leon, Emilio Isaac (March 2, 2026). "From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs". Electronics. 15 (5): 1048. doi:10.3390/electronics15051048.
  3. ↑ Lavagno, Luciano; Martin, Grant E.; Markov, Igor L.; Scheffer, Louis K., eds. (2026). Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. Vol. 2 (3rd ed.). CRC Press. Retrieved September 18, 2026.
  4. ↑ "OpenROAD Flow Scripts User Guide". GitHub. OpenROAD Project. Retrieved September 18, 2026.
  5. ↑ Iyer, Indira; Liberty, Matt; Bandeira, Vitor; Rovinski, Austin; Luar, Jack (January 22, 2024). "OpenROAD - An Open-Source, Autonomous RTL-GDSII Flow for Chip Design". UCSC Open Source Program Office. University of California, Santa Cruz. Retrieved September 18, 2026.
  6. ↑ "Hammer: Highly Agile Masks Made Effortlessly from RTL". GitHub. UC Berkeley Architecture Research. Retrieved September 18, 2026.
  7. ↑ "OpenFASoC". GitHub. OpenFASoC. Retrieved September 18, 2026.
  8. ↑ "OpenLane". GitHub. Retrieved September 18, 2026.
  9. ↑ "OpenROAD Flow Scripts". GitHub. OpenROAD Project. Retrieved September 18, 2026.
  10. ↑ "OSS CAD Suite". GitHub. YosysHQ. Retrieved September 18, 2026.
  11. ↑ "SiliconCompiler". GitHub. SiliconCompiler. Retrieved September 18, 2026.
  12. ↑ "Amaranth HDL". GitHub. Amaranth HDL. Retrieved September 18, 2026.
  13. ↑ "Chisel". Chisel. CHIPS Alliance. Retrieved September 18, 2026.
  14. ↑ "Chisel". GitHub. CHIPS Alliance. Retrieved September 18, 2026.
  15. ↑ "Clash". Clash. Retrieved September 18, 2026.
  16. ↑ "Clash Compiler". GitHub. Clash Language. Retrieved September 18, 2026.
  17. ↑ "MyHDL". GitHub. MyHDL. Retrieved September 18, 2026.
  18. ↑ "PyRTL". GitHub. UCSB Architecture Laboratory. Retrieved September 18, 2026.
  19. ↑ "SpinalHDL". GitHub. SpinalHDL. Retrieved September 18, 2026.
  20. ↑ "CIRCT: Circuit IR Compilers and Tools". GitHub. LLVM Project. Retrieved September 18, 2026.
  21. ↑ "slang". GitHub. Retrieved September 18, 2026.
  22. ↑ "Surelog". GitHub. CHIPS Alliance. Retrieved September 18, 2026.
  23. ↑ "Verible". GitHub. CHIPS Alliance. Retrieved September 18, 2026.
  24. ↑ "PandA Bambu HLS Framework". GitHub. Politecnico di Milano. Retrieved September 18, 2026.
  25. ↑ "Yosys Open SYnthesis Suite". GitHub. YosysHQ. Retrieved September 18, 2026.
  26. ↑ "Welcome to cocotb". cocotb documentation. Retrieved September 18, 2026.
  27. ↑ "About". gem5. Retrieved September 18, 2026.
  28. ↑ "gem5/gem5". GitHub. gem5. Retrieved September 18, 2026.
  29. ↑ "GHDL". GitHub. Retrieved September 18, 2026.
  30. ↑ "Icarus Verilog". GitHub. Retrieved September 18, 2026.
  31. ↑ "SymbiYosys". GitHub. Retrieved September 18, 2026.
  32. ↑ "Verilator". GitHub. CHIPS Alliance. Retrieved September 18, 2026.
  33. ↑ "GTKWave". GitHub. Retrieved September 18, 2026.
  34. ↑ "OpenCache". GitHub. VLSI Design and Automation Group. Retrieved September 18, 2026.
  35. ↑ "OpenRAM". GitHub. VLSI Design and Automation Group. Retrieved September 18, 2026.
  36. ↑ "Basic ROM Usage". GitHub. VLSI Design and Automation Group. Retrieved September 18, 2026.
  37. ↑ "OpenTCAM". GitHub. Retrieved September 18, 2026.
  38. ↑ "nextpnr". GitHub. YosysHQ. Retrieved September 18, 2026.
  39. ↑ "Verilog to Routing". GitHub. Retrieved September 18, 2026.
  40. ↑ "iEDA". GitHub. OSCC Project. Retrieved September 18, 2026.
  41. ↑ Li, Xingquan; Huang, Zengrong; Tao, Simin (2024). iEDA: An Open-source Infrastructure of EDA. 2024 29th Asia and South Pacific Design Automation Conference. pp. 77–82.
  42. ↑ "OpenROAD". GitHub. OpenROAD Project. Retrieved September 18, 2026.
  43. ↑ "OpenSTA". GitHub. OpenROAD Project. Retrieved September 18, 2026.
  44. ↑ "OpenTimer". GitHub. Retrieved September 18, 2026.
  45. ↑ "GDSFactory". GitHub. GDSFactory. Retrieved September 18, 2026.
  46. ↑ "Gdstk". GitHub. Retrieved September 18, 2026.
  47. ↑ "KFactory". GitHub. GDSFactory. Retrieved September 18, 2026.
  48. ↑ "PHIDL". GitHub. Retrieved September 18, 2026.
  49. ↑ McCaughan, Adam N.; Tait, Alexander N.; Buckley, Sonia M.; Oh, Dylan M.; Chiles, Jeffrey T.; Shainline, Jeffrey M.; Nam, Sae Woo (2021). "PHIDL: Python-based layout and geometry creation for nanolithography". Journal of Vacuum Science & Technology B. 39 (6): 062601. arXiv:2103.01152. doi:10.1116/6.0001203.
  50. ↑ "Electric". GNU Project. Free Software Foundation. Retrieved September 18, 2026.
  51. ↑ "KLayout". GitHub. Retrieved September 18, 2026.
  52. ↑ "Magic VLSI Layout Tool". GitHub. Retrieved September 18, 2026.
  53. ↑ "Netgen". GitHub. Retrieved September 18, 2026.
  54. ↑ Sanchez, Juan E. (2022). "DEVSIM: A TCAD Semiconductor Device Simulator". Journal of Open Source Software. 7 (70): 3898. doi:10.21105/joss.03898.
  55. ↑ "ngspice". GitHub. Retrieved September 18, 2026.
  56. ↑ "Oregano". GitHub. Retrieved September 18, 2026.
  57. ↑ "Qucs-S". GitHub. Retrieved September 18, 2026.
  58. ↑ "XCircuit". GitHub. R. Timothy Edwards. Retrieved September 18, 2026.
  59. ↑ "Xschem". GitHub. Retrieved September 18, 2026.
  60. ↑ "Xyce Parallel Electronic Simulator". GitHub. Sandia National Laboratories. Retrieved September 18, 2026.
  61. ↑ "Fritzing desktop application". GitHub. Fritzing. Retrieved September 18, 2026.
  62. ↑ "Horizon EDA". GitHub. Horizon EDA. Retrieved September 18, 2026.
  63. ↑ "KiCad Source Code". GitLab. KiCad. Retrieved September 18, 2026.
  64. ↑ "LibrePCB". GitHub. LibrePCB. Retrieved September 18, 2026.
  65. ↑ "pcb-rnd". pcb-rnd. Retrieved September 18, 2026.
  66. ↑ "gerber2ems". GitHub. Antmicro. Retrieved September 18, 2026.
  67. ↑ "openEMS". GitHub. Retrieved September 18, 2026.