Graphics Core Next

GCN
AMD GCN Architecture Logo
DesignerAMD
Bits32-bit and 64-bit
Introduced2012
DesignSIMT
TypeRegister–memory (LDS/GDS), Load-store (Scalar/Vector)
EncodingVariable (4-byte or 8-byte)
BranchingVector condition code, Scalar condition code, Execute mask
EndiannessLittle
Page size4 KB
ExtensionsFLAT, SMEM, SDWA, DPP, PERMUTE, F16, VOP3P, SCRATCH, GLOBAL
OpenNo
PredecessorTeraScale
SuccessorRDNA, CDNA
Registers
General-purposeVariable (8 to 104 visible to each scalar unit)
Floating-pointVariable (4 to 256 visible to each vector unit)

GCN (also known as Graphics Core Next) is a series of graphics processor architectures developed by AMD. GCN was introduced in 2012 as a non-VLIW redesign of AMD's TeraScale architecture.

Introduction

CPUs typically expose programming models architecturally equivalent to the classic RISC pipeline where individual scalar instructions are fetched, decoded, and executed sequentially.

In contrast, GPUs typically expose an explicitly data-parallel programming model. In both GCN and TeraScale, programs are organized as parallel threads, where each thread considers different elements of an input data set.

Threads are executed in hardware in groups of 64 called a "wavefront". Wavefronts differ from a classic RISC pipeline in that all threads in the wavefront share a single program counter, and execute in parallel and in lock-step. The ability to issue 64 operations per instruction fetch significantly reduces area and power requirements.

History

In AMD's previous TeraScale design, vector ALUs executed 16 groups of 4 scalar operations from a single wavefront per cycle. Each operation's placement within a group is determined statically, and correspond to TeraScale VLIW instruction slots. Effective utilization of all available slots in each instruction depends on a compiler's ability to find independent operations within a single wavefront.

The GCN architecture removes the instruction slot concept completely: each (non-VLIW) instruction instead encodes a single operation. A single vector unit now executes 16 scalar operations from 4 different wavefronts per cycle.

AMD's goal in making this change was to make the performance and occupancy of GCN dependent on wavefront-parallelism, contrast to TeraScale which is dependent on a compiler's ability to find independent operations within a single wavefront.

Instruction set

The GCN instruction set is owned by AMD and was developed specifically for GPUs.

Family Document New Features/Changes Example
Products
Name Rev.
Southern Islands Southern Islands Series Instruction Set Architecture 1.1 Radeon HD 7970
Radeon HD 8970
Southern Islands Series Instruction Set Architecture 1.4
Sea Islands Sea Islands Series Instruction Set Architecture 1.0 FLAT instructions,
thread-private memory,
96-bit load/store,
conditional debug instructions,
F64 rounding instructions		 Radeon R9 290X
Sea Islands Series Instruction Set Architecture 1.3
Volcanic Islands,
Arctic Islands		 Graphics Core Next Architecture, Generation 3 1.0 binary-incompatible
with previous versions,
16-bit floating-point math,
scalar memory writes,
VGPR indexing,
DPP instructions,
SDWA instructions,
permute instructions
 Radeon R9 390
Radeon RX 480
Radeon RX 580
Graphics Core Next Architecture, Generation 3 1.1
Vega "Vega" Instruction Set Architecture packed 16-bit arithmetic,
scalar memory atomics
SCRATCH instructions,
GLOBAL instructions		 Radeon RX Vega 64
Vega 7nm "Vega" 7nm Instruction Set Architecture packed dot product Radeon Instinct MI50
Radeon VII

Compiler Support

LLVM has code generation support for all GCN variants.

Mesa uses the Mesa-internal ACO compiler for GCN code generation.

GCC implements code generation for Vega and Vega 7nm. Older versions of GCC previously included code generation support for Fiji (Volcanic Islands), though this was removed in GCC 15. All other GCN variants are unsupported. GCC 10 introduced offloading via OpenMP and OpenACC.

Architecture

Command processing

GCN command processing: Each Asynchronous Compute Engines (ACE) can parse incoming commands and dispatch work to the Compute Units (CUs). Each ACE can manage up to 8 independent queues. The ACEs can operate in parallel with the graphics command processor and two DMA engines. The graphics command processor handles graphics queues, the ACEs handle compute queues, and the DMA engines handle copy queues. Each queue can dispatch work items without waiting for other tasks to complete, allowing independent command streams to be interleaved on the GPU's Shader.

Graphics Command Processor

The Graphics Command Processor (GCP) is a functional unit of the GCN microarchitecture. Among other tasks, it is responsible for the handling of asynchronous shaders.[failed verification]

Asynchronous Compute Engine

The Asynchronous Compute Engine (ACE) is a distinct functional block serving computing purposes, whose purpose is similar to that of the Graphics Command Processor.[ambiguous]

Schedulers

Since the third iteration of GCN, the hardware contains two schedulers: one to schedule "wavefronts" during shader execution (the CU Scheduler, or Compute Unit Scheduler) and the other to schedule execution of draw and compute queues. The latter helps performance by executing compute operations when the compute units (CUs) are underutilized due to graphics commands limited by fixed function pipeline speed or bandwidth. This functionality is known as Async Compute.

For a given shader, the GPU drivers may also schedule instructions on the CPU to minimize latency.

Geometric processor

Geometry processor

The geometry processor contains a Geometry Assembler, a Tesselator, and a Vertex Assembler.

The Tesselator is capable of doing tessellation in hardware as defined by Direct3D 11 and OpenGL 4.6.

Compute units

One compute unit (CU) combines 64 shader processors with 4 texture mapping units (TMUs). The compute units are separate from, but feed into, the render output units (ROPs). Each compute unit consists of the following:

Four Compute units are wired to share a 16KiB L1 instruction cache and a 32KiB L1 data cache, both of which are read-only. A SIMD-VU operates on 16 elements at a time (per cycle), while a SU can operate on one a time (one/cycle). In addition, the SU handles some other operations, such as branching.

Every SIMD-VU has some private memory where it stores its registers. There are two types of registers: scalar registers (S0, S1, etc.), which hold 4 bytes number each, and vector registers (V0, V1, etc.), which each represent a set of 64 4-byte numbers. On the vector registers, every operation is done in parallel on the 64 numbers. which correspond to 64 inputs. For example, it may work on 64 different pixels at a time (for each of them the inputs are slightly different, and thus you get slightly different color at the end).

Every SIMD-VU has room for 512 scalar registers and 256 vector registers.

AMD has claimed that each GCN compute unit (CU) has 64 KiB Local Data Share (LDS).

CU scheduler

The CU scheduler is the hardware functional block, choosing which wavefronts the SIMD-VU executes. It picks one SIMD-VU per cycle for scheduling. This is not to be confused with other hardware or software schedulers.

Wavefront

A shader is a small program written in GLSL that performs graphics processing, and a kernel is a small program written in OpenCL that performs GPGPU processing. These processes don't need that many registers, but they do need to load data from system or graphics memory. This operation comes with significant latency. AMD and Nvidia chose similar approaches to hide this unavoidable latency: the grouping of multiple threads. AMD calls such a group a "wavefront", whereas Nvidia calls it a "warp". A group of threads is the most basic unit of scheduling of GPUs that implement this approach to hide latency. It is the minimum size of the data processed in SIMD fashion, the smallest executable unit of code, and the way to processes a single instruction over all of the threads in it at the same time.

In all GCN GPUs, a "wavefront" consists of 64 threads, and in all Nvidia GPUs, a "warp" consists of 32 threads.

AMD's solution is to attribute multiple wavefronts to each SIMD-VU. The hardware distributes the registers to the different wavefronts, and when one wavefront is waiting on some result, which lies in memory, the CU Scheduler assigns the SIMD-VU another wavefront. Wavefronts are attributed per SIMD-VU. SIMD-VUs do not exchange wavefronts. A maximum of 10 wavefronts can be attributed per SIMD-VU (thus 40 per CU).

AMD CodeXL shows tables with the relationship between number of SGPRs and VGPRs to the number of wavefronts, but essentially, for SGPRS it is between 104 and 512 per number of wavefronts, and for VGPRS it is 256 per number of wavefronts.

Note that in conjunction with the SSE instructions, this concept of the most basic level of parallelism is often called a "vector width". The vector width is characterized by the total number of bits in it.

SIMD Vector Unit

Each SIMD Vector Unit has:

  • a 16-lane integer and floating point vector Arithmetic Logic Unit (ALU)
  • 64 KiB Vector General Purpose Register (VGPR) file
  • 10× 48-bit Program Counters
  • Instruction buffer for 10 wavefronts (each wavefront is a group of 64 threads, or the size of one logical VGPR)
  • A 64-thread wavefront issues to a 16-lane SIMD Unit over four cycles

Each SIMD-VU has 10 wavefront instruction buffers, and it takes 4 cycles to execute one wavefront.

Audio and video acceleration blocks

Many implementations of GCN are typically accompanied by several of AMD's other ASIC blocks. Including but not limited to the Unified Video Decoder, Video Coding Engine, and AMD TrueAudio.

Video Coding Engine

The Video Coding Engine is a video encoding ASIC, first introduced with the Radeon HD 7000 series.

The initial version of the VCE added support for encoding I and P frames H.264 in the YUV420 pixel format, along with SVE temporal encode and Display Encode Mode, while the second version added B-frame support for YUV420 and YUV444 I-frames.

VCE 3.0 formed a part of the third generation of GCN, adding high-quality video scaling and the HEVC (H.265) codec.

VCE 4.0 was part of the Vega architecture, and was subsequently succeeded by Video Core Next.

Unified virtual memory

In a preview in 2011, AnandTech wrote about the unified virtual memory, supported by Graphics Core Next.

Heterogeneous System Architecture (HSA)

GCN includes special purpose function blocks to be used by HSA. Support for these function blocks is available through amdkfd since Linux kernel 3.19.

Some of the specific HSA features implemented in the hardware need support from the operating system's kernel (its subsystems) and/or from specific device drivers. For example, in July 2014, AMD published a set of 83 patches to be merged into Linux kernel mainline 3.17 for supporting their Graphics Core Next-based Radeon graphics cards. The so-called HSA kernel driver resides in the directory /drivers/gpu/hsa, while the DRM graphics device drivers reside in /drivers/gpu/drm and augment the already existing DRM drivers for Radeon cards. This very first implementation focuses on a single "Kaveri" APU and works alongside the existing Radeon kernel graphics driver (kgd).

Hardware schedulers

Hardware schedulers are used to perform scheduling and offload the assignment of compute queues to the ACEs from the driver to hardware, by buffering these queues until there is at least one empty queue in at least one ACE. This causes the HWS to immediately assign buffered queues to the ACEs until all queues are full or there are no more queues to safely assign.

Part of the scheduling work performed includes prioritized queues which allow critical tasks to run at a higher priority than other tasks without requiring the lower priority tasks to be preempted to run the high priority task, therefore allowing the tasks to run concurrently with the high priority tasks scheduled to hog the GPU as much as possible while letting other tasks use the resources that the high priority tasks are not using. These are essentially Asynchronous Compute Engines that lack dispatch controllers. They were first introduced in the fourth generation GCN microarchitecture, but were present in the third generation GCN microarchitecture for internal testing purposes. A driver update has enabled the hardware schedulers in third generation GCN parts for production use.

Primitive Discard Accelerator

This unit discards degenerate triangles before they enter the vertex shader and triangles that do not cover any fragments before they enter the fragment shader. This unit was introduced with the fourth generation GCN microarchitecture.

Generations

Graphics Core Next 1

AMD Graphics Core Next 1
Release dateJanuary 2012; 14 years ago (January 2012)
History
PredecessorTeraScale 3
SuccessorGraphics Core Next 2
Support status
Unsupported since mid-2022 (final Windows driver version 22.6.1 for Windows 7 and 10)

The GCN 1 microarchitecture was used in several Radeon HD 7000 series graphics cards.

Die shot of the Tahiti GPU used in Radeon HD 7950 GHz Edition graphics cards

There are Asynchronous Compute Engines controlling computation and dispatching.

ZeroCore Power

ZeroCore Power is a long idle power saving technology, shutting off functional units of the GPU when not in use. AMD ZeroCore Power technology supplements AMD PowerTune.

Chips

Discrete GPUs (Southern Islands family):

  • Hainan
  • Oland
  • Cape Verde
  • Pitcairn
  • Tahiti

Graphics Core Next 2

AMD Graphics Core Next 2
Release dateSeptember 2013; 13 years ago (September 2013)
History
PredecessorGraphics Core Next 1
SuccessorGraphics Core Next 3
Support status
Unsupported since mid-2022 (final Windows driver version 22.6.1 for Windows 7 and 10)
AMD PowerTune "Bonaire"
Die shot of the Hawaii GPU used in Radeon R9 290 graphics cards

The 2nd generation of GCN was introduced with the Radeon HD 7790 and is also found in the Radeon HD 8770, R7 260/260X, R9 290/290X, R9 295X2, R7 360, and R9 390/390X, as well as Steamroller-based desktop "Kaveri" APUs and mobile "Kaveri" APUs and in the Puma-based "Beema" and "Mullins" APUs. It has multiple advantages over the original GCN, including FreeSync support, AMD TrueAudio and a revised version of AMD PowerTune technology.

GCN 2nd generation introduced an entity called "Shader Engine" (SE)[citation needed]. A Shader Engine comprises one geometry processor, up to 44 CUs (Hawaii chip), rasterizers, ROPs, and L1 cache. Not part of a Shader Engine is the Graphics Command Processor, the 8 ACEs, the L2 cache and memory controllers as well as the audio and video accelerators, the display controllers, the 2 DMA controllers and the PCIe interface.

The A10-7850K "Kaveri" contains 8 CUs (compute units) and 8 Asynchronous Compute Engines for independent scheduling and work item dispatching.

At AMD Developer Summit (APU) in November 2013 Michael Mantor presented the Radeon R9 290X.

Chips

Discrete GPUs (Sea Islands family):

  • Bonaire
  • Hawaii

integrated into APUs:

  • Temash
  • Kabini
  • Liverpool (i.e. the APU found in the PlayStation 4)
  • Durango (i.e. the APU found in the Xbox One and Xbox One S)
  • Kaveri
  • Godavari
  • Mullins
  • Beema
  • Carrizo-L

Graphics Core Next 3

AMD Graphics Core Next 3
Release dateJune 2015; 11 years ago (June 2015)
History
PredecessorGraphics Core Next 2
SuccessorGraphics Core Next 4
Support status
Supported, with less regular Windows driver update schedule
Die shot of the Fiji GPU used in Radeon R9 Nano graphics cards

GCN 3rd generation was introduced in 2014 with the Radeon R9 285 and R9 M295X, which have the "Tonga" GPU. It features improved tessellation performance, lossless delta color compression to reduce memory bandwidth usage, an updated and more efficient instruction set, a new high quality scaler for video, HEVC encoding (VCE 3.0) and HEVC decoding (UVD 6.0), and a new multimedia engine (video encoder/decoder). Delta color compression is supported in Mesa. However, its double precision performance is worse compared to previous generation.[failed verification]

Chips

discrete GPUs:

  • Tonga (Volcanic Islands family), comes with UVD 5.0 (Unified Video Decoder)
  • Fiji (Pirate Islands family), comes with UVD 6.0 and High Bandwidth Memory (HBM 1)

integrated into APUs:

  • Carrizo, comes with UVD 6.0
  • Bristol Ridge
  • Stoney Ridge

Graphics Core Next 4

AMD Graphics Core Next 4
Release dateJune 2016; 10 years ago (June 2016)
History
PredecessorGraphics Core Next 3
SuccessorGraphics Core Next 5
Support status
Supported, with less regular Windows driver update schedule
Die shot of the Polaris 11 GPU used in Radeon RX 460 graphics cards
Die shot of the Polaris 10 GPU used in Radeon RX 470 graphics cards

GPUs of the Arctic Islands-family were introduced in Q2 of 2016 with the AMD Radeon 400 series. The 3D-engine (i.e. GCA (Graphics and Compute array) or GFX) is identical to that found in the Tonga-chips. But Polaris feature a newer Display Controller engine, UVD version 6.3, etc.

All Polaris-based chips other than the Polaris 30 are produced on the 14 nm FinFET process, developed by Samsung Electronics and licensed to GlobalFoundries. The slightly newer refreshed Polaris 30 is built on the 12 nm LP FinFET process node, developed by Samsung and GlobalFoundries. The fourth generation GCN instruction set architecture is compatible with the third generation. It is an optimization for 14 nm FinFET process enabling higher GPU clock speeds than with the 3rd GCN generation. Architectural improvements include new hardware schedulers, a new primitive discard accelerator, a new display controller, and an updated UVD that can decode HEVC at 4K resolutions at 60 frames per second with 10 bits per color channel.

Chips

discrete GPUs:

  • Polaris 10 (also codenamed Ellesmere) found on "Radeon RX 470" and "Radeon RX 480"-branded graphics cards
  • Polaris 11 (also codenamed Baffin) found on "Radeon RX 460"-branded graphics cards (also Radeon RX 560D)
  • Polaris 12 (also codenamed Lexa) found on "Radeon RX 550" and "Radeon RX 540"-branded graphics cards
  • Polaris 20, which is a refreshed (14 nm LPP Samsung/GloFo FinFET process) Polaris 10 with higher clocks, used for "Radeon RX 570" and "Radeon RX 580"-branded graphics cards
  • Polaris 21, which is a refreshed (14 nm LPP Samsung/GloFo FinFET process) Polaris 11, used for "Radeon RX 560"-branded graphics cards
  • Polaris 22, found on "Radeon RX Vega M GH" and "Radeon RX Vega M GL"-branded graphics cards (as part of Kaby Lake-G)
  • Polaris 23, which is a refreshed (14 nm LPP Samsung/GloFo FinFET process) Polaris 12, used for "Radeon Pro WX 3200" and "Radeon RX 540X"-branded graphics cards (also Radeon RX 640)
  • Polaris 30, which is a refreshed (12 nm LP GloFo FinFET process) Polaris 20 with higher clocks, used for "Radeon RX 590"-branded graphics cards

In addition to dedicated GPUs, Polaris is utilized in the APUs of the PlayStation 4 Pro and Xbox One X, titled "Neo" and "Scorpio", respectively.

Precision Performance

FP64 performance of all GCN 4th generation GPUs is 1/16 of FP32 performance.

Graphics Core Next 5

AMD Graphics Core Next 5
Release dateJune 2017; 9 years ago (June 2017)
History
PredecessorGraphics Core Next 4
SuccessorCDNA 1, RDNA 1
Support status
Supported, with less regular Windows driver update schedule
Die shot of the Vega 10 GPU used in Radeon RX Vega 64 graphics cards

AMD began releasing details of their next generation of GCN Architecture, termed the 'Next-Generation Compute Unit', in January 2017. The new design was expected to increase instructions per clock, higher clock speeds, support for HBM2, a larger memory address space. The discrete graphics chipsets also include "HBCC (High Bandwidth Cache Controller)", but not when integrated into APUs. Additionally, the new chips were expected to include improvements in the Rasterisation and Render output units. The stream processors are heavily modified from the previous generations to support packed math Rapid Pack Math technology for 8-bit, 16-bit, and 32-bit numbers. With this there is a significant performance advantage when lower precision is acceptable (for example: processing two half-precision numbers at the same rate as a single single precision number).

Nvidia introduced tile-based rasterization and binning with Maxwell, and this was a big reason for Maxwell's efficiency increase. In January, AnandTech assumed that Vega would finally catch up with Nvidia regarding energy efficiency optimizations due to the new "DSBR (Draw Stream Binning Rasterizer)" to be introduced with Vega.

It also added support for a new shader stage – Primitive Shaders. Primitive shaders provide more flexible geometry processing and replace the vertex and geometry shaders in a rendering pipeline. As of December 2018, the Primitive shaders can't be used because required API changes are yet to be done.

Vega 10 and Vega 12 use the 14 nm FinFET process, developed by Samsung Electronics and licensed to GlobalFoundries. Vega 20 uses the 7 nm FinFET process developed by TSMC.

Chips

discrete GPUs:

  • Vega 10 (14 nm Samsung/GloFo FinFET process) (also codenamed Greenland) found on "Radeon RX Vega 64", "Radeon RX Vega 56", "Radeon Vega Frontier Edition", "Radeon Pro V340", Radeon Pro WX 9100, and Radeon Pro WX 8200 graphics cards
  • Vega 12 (14 nm Samsung/GloFo FinFET process) found on "Radeon Pro Vega 20" and "Radeon Pro Vega 16"-branded mobile graphics cards
  • Vega 20 (7 nm TSMC FinFET process) found on "Radeon Instinct MI50" and "Radeon Instinct MI60"-branded accelerator cards, "Radeon Pro Vega II", and "Radeon VII"-branded graphics cards.

integrated into APUs:

  • Raven Ridge came with VCN 1 which supersedes VCE and UVD and allows full fixed-function VP9 decode.
  • Picasso
  • Renoir
  • Cezanne

Precision performance

Double-precision floating-point (FP64) performance of all GCN 5th generation GPUs, except for Vega 20, is one-sixteenth of FP32 performance. For Vega 20 with Radeon Instinct this is half of FP32 performance. For Vega 20 with Radeon VII this is a quarter of FP32 performance. All GCN 5th generation GPUs support half-precision floating-point (FP16) calculations which is twice of FP32 performance.

Comparison of GCN GPUs

Generation GCN 1 GCN 2 GCN 3 GCN 4 GCN 5
Series (Family) Southern IslandsSea IslandsVolcanic IslandsArctic IslandsVegaVega 7nm
Die Tahiti Pitcairn Cape Verde Oland Hainan Bonaire Hawaii Topaz Tonga Fiji Ellesmere Baffin Lexa VegaM Vega 10 Vega 12 Vega 20
Code name ? ? ? Tiran ? ? Ibiza Iceland ? ? Polaris 10 Polaris 11 Polaris 12 Polaris 22 Greenland Treasure Refresh Moonshot
Variant(s) New Zealand
Malta		 Wimbledon
Curaçao
Neptune
Trinidad		 Chelsea
Heathrow
Venus
Tropo		 Mars
Opal
Litho		 Sun
Jet
Exo
Banks		 Saturn
Tobago
Strato
Emerald		 Vesuvius
Grenada		 Meso
Weston
Polaris 24		 Amethyst
Antigua		 Capsaicin Polaris 21 Polaris 23 N/a N/a N/a N/a N/a
Fab TSMC 28 nm GlobalFoundries 14 nm / 12 nm (Polaris 30) TSMC 7 nm
Die size (mm2) 352 / 365 (Malta)2121237756160438125366596232123103208495~250331
Transistors (million) 4,3132,8001,5009506902,0806,2001,5505,0008,9005,7003,0002,2005,00012,500Unknown13,230
Transistor density (MTr/mm2) 12.3 / 12.8 (Malta)13.212.212.313.014.212.413.714.924.624.421.424.025.3Unknown40.0
Asynchronous compute engines 28?84
Geometry engines 212N/a?N/a424
Shader engines N/a4?424N/a
Hardware schedulers N/a2
Compute units 322010 / 8 (Chelsea)65 / 6 (Jet)14446326436161024642064
Stream processors 20481280640 / 512 (Chelsea)384320 / 384 (Jet)896281638420484096230410246401536409612804096
Texture mapping units 1288040 / 32 (Chelsea)2420 / 24 (Jet)561762412825614464409625680256
Render output units 321681664832643216643264
Z/Stencil OPS 12864166425616128256N/a
L1 cache (KB) 16 per Compute unit (CU)
L2 cache (KB) 768512256128 / 256 (Jet)2561024256768204810245121024409610244096
Display Core Engine 6.06.4N/a8.28.5N/a10.011.212.012.1
Unified Video Decoder 3.24.0N/a4.2N/a5.06.06.37.07.2
Video Coding Engine 1.0N/a2.0N/a3.03.44.04.1
Launch Dec 2011 Mar 2012 Feb 2012 Jan 2013 May 2015 Mar 2013 Oct 2013 2014 Aug 2014 Jun 2015 Jun 2016 Aug 2016 Apr 2017 Feb 2018 Jun 2017 Nov 2018 Nov 2018
Notes mobile/OEMmobile/OEMmobile/OEMmobile

See also

Notes

  1. ↑ Sequential from the perspective of externally-visible architectural state. Modern CPUs may be superscalar or execute instructions out of order internally, but are still required to resolve architectural state as if execution were sequential (increasing hardware/design complexity).
  2. ↑ Contrast to superscalar and multi-core CPU designs, which require more power, more area, and more design complexity to complete the same operations at the same rate.
  3. ↑ Earlier versions of TeraScale included a 5th slot, which was dedicated to transcendental operations. AMD removed the 5th slot as an optimization, as it found the transcendental unit was heavily under-used in practice.
  4. ↑ Contains several documentation bugs (e.g: incorrect bit definitions); defines an S_MOV_FED_B32 instruction not mentioned in any other documents
  5. ↑ "AMD Radeon HD 7970" (Tahiti XT), "AMD Radeon HD 7870" (Pitcairn XT), "AMD Radeon HD 7770" (Cape Verde XT) are given as examples of "GCN" GPUs in AMD Graphics Cores Next (GCN) Architecture on page 13-15.
  6. ↑ "Tonga", "Fiji", and "Antigua" are explicitly mentioned as examples of "3rd-generation GCN solutions" in Radeon: Dissecting the Polaris Architecture on page 9.
  7. ↑ Old code names such as Treasure (Lexa) or Hawaii Refresh (Ellesmere) are not listed.
  8. ↑ Initial launch date. Launch dates of variant chips such as Polaris 20 (April 2017) are not listed.

References

Citations

  1. ↑ "The AMD GCN Architecture A Crash Course". Archived from the original on August 19, 2014.
  2. ↑ Christopher J. Hughes (2015). Margaret Martonosi (ed.). Single-Instruction Multple-Data Execution (PDF). Synthesis Lectures on Computer Architecture. Morgan & Claypool Publishers. pp. 9, 12, 13, 16. ISBN 9781627057646. Retrieved October 10, 2026.
  3. 1 2 3 "AMD Graphics Cores Next (GCN) Architecture" (PDF). Archived from the original (PDF) on May 1, 2014. Retrieved October 8, 2026.
  4. ↑ "Developer Guides & Manuals". Archived from the original on July 1, 2014.
  5. 1 2 "User Guide for AMDGPU Backend: Processors". Retrieved October 8, 2026.
  6. ↑ "AMD community forums". Community.amd.com. July 15, 2016.
  7. ↑ "User Guide for AMDGPU Backend".
  8. ↑ "radv: enable ACO by default". Retrieved October 9, 2026.
  9. ↑ "radeonsi: enable ACO by default". Retrieved October 9, 2026.
  10. ↑ "AMD GCN Options". Retrieved October 9, 2026.
  11. ↑ "GCC 9 Release Series Changes, New Features, and Fixes". Retrieved November 13, 2019.
  12. ↑ "GCC 15 Release Series Changes, New Features, and Fixes". Retrieved October 9, 2026.
  13. ↑ "AMD GCN Offloading Support". Retrieved October 9, 2026.
  14. ↑ Smith, Ryan. "AMD Dives Deep On Asynchronous Shading". Anandtech.com. Archived from the original on April 2, 2015.
  15. ↑ "Conformant Products". Khronos.org. December 16, 2018.
  16. ↑ Compute Cores Whitepaper (PDF). AMD. 2014. p. 5.
  17. 1 2 Smith, Ryan (December 21, 2011). "AMD's Graphics Core Next Preview". Anandtech.com. Retrieved April 18, 2017.{{cite news}}: CS1 maint: deprecated archival service (link)
  18. ↑ "AMD's Graphics Core Next (GCN) Architecture" (PDF). TechPowerUp. Retrieved February 26, 2024.
  19. 1 2 Mantor, Michael; Houston, Mike (June 15, 2011). "AMD Graphics Core Next" (PDF). AMD. p. 40. Retrieved July 15, 2014. Asynchronous Compute Engine (ACE)
  20. ↑ "Optimizing GPU occupancy and resource usage with large thread groups". AMD GPUOpen. Retrieved January 1, 2024.
  21. ↑ "White Paper AMD UnifiedVideoDecoder (UVD)" (PDF). June 15, 2012. Retrieved May 20, 2017.
  22. 1 2 "Not Just A New Architecture, But New Features Too". AnandTech. December 21, 2011. Archived from the original on June 19, 2011. Retrieved July 11, 2014.
  23. ↑ "Kaveri microarchitecture". SemiAccurate. January 15, 2014.
  24. ↑ Airlie, Dave (November 26, 2014). "Merge AMDKFD". freedesktop.org. Retrieved January 21, 2015.
  25. ↑ "/drivers/gpu/drm". Kernel.org.
  26. ↑ "[PATCH 00/83] AMD HSA kernel driver". LKML. July 10, 2014. Retrieved July 11, 2014.
  27. 1 2 3 4 5 Angelini, Chris (June 29, 2016). "AMD Radeon RX 480 8GB Review". Tom's Hardware. p. 1. Retrieved August 11, 2016.
  28. ↑ "Dissecting the Polaris Architecture" (PDF). 2016. Archived from the original (PDF) on September 20, 2016. Retrieved August 12, 2016.
  29. ↑ Shrout, Ryan (June 29, 2016). "The AMD Radeon RX 480 Review – The Polaris Promise". PC Perspective. p. 2. Archived from the original on October 10, 2016. Retrieved August 12, 2016.
  30. 1 2 Smith, Ryan (June 29, 2016). "The AMD Radeon RX 480 Preview: Polaris Makes Its Mainstream Mark". AnandTech. p. 3. Archived from the original on July 2, 2016. Retrieved August 11, 2016.
  31. ↑ "AMD Radeon HD 7000 Series to be PCI-Express 3.0 Compliant". TechPowerUp. Retrieved July 21, 2011.
  32. ↑ "AMD Details Next Gen. GPU Architecture". Archived from the original on March 28, 2012. Retrieved August 3, 2011.
  33. ↑ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, archived from the original (PDF) on January 18, 2023, retrieved August 13, 2016
  34. ↑ "AMD's Graphics Core Next Preview: AMD's New GPU, Architected For Compute". AnandTech. December 21, 2011. Retrieved July 15, 2014. AMD's new Asynchronous Compute Engines serve as the command processors for compute operations on GCN. The principal purpose of ACEs will be to accept work and to dispatch it off to the CUs for processing.{{cite web}}: CS1 maint: deprecated archival service (link)
  35. ↑ "Managing Idle Power: Introducing ZeroCore Power". AnandTech.com. December 22, 2011. Archived from the original on January 7, 2012. Retrieved April 29, 2015.
  36. ↑ "AMD's Kaveri A10-7850K tested". AnandTech. January 14, 2014. Archived from the original on January 16, 2014. Retrieved July 7, 2014.
  37. ↑ "AMD Radeon R9-290X". November 21, 2013.
  38. ↑ "Carrizo Overview". Images.anandtech.com. Archived from the original (PNG) on March 4, 2016. Retrieved July 20, 2018.
  39. ↑ "Add DCC Support". Freedesktop.org. October 11, 2015.
  40. ↑ Smith, Ryan (September 10, 2014). "AMD Radeon R9 285 Review". Anandtech.com. Archived from the original on September 12, 2014. Retrieved March 13, 2017.
  41. 1 2 Cutress, Ian (June 1, 2016). "AMD Announces 7th Generation APU". Anandtech.com. Archived from the original on June 2, 2016. Retrieved June 1, 2016.
  42. ↑ "RadeonFeature". www.x.org.
  43. ↑ "Radeon Technologies Group – January 2016 – AMD Polaris Architecture". Guru3d.com.
  44. 1 2 Smith, Ryan (January 5, 2017). "The AMD Vega Architecture Teaser: Higher IPC, Tiling, & More, coming in H1'2017". Anandtech.com. Archived from the original on January 6, 2017. Retrieved January 10, 2017.
  45. ↑ WhyCry (March 24, 2016). "AMD confirms Polaris 10 is Ellesmere and Polaris 11 is Baffin". VideoCardz. Retrieved April 8, 2016.
  46. ↑ "Fast vollständige Hardware-Daten zu AMDs Radeon RX 500 Serie geleakt". www.3dcenter.org.
  47. ↑ "AMD Polaris 23". TechPowerUp. Retrieved May 12, 2022.
  48. ↑ Oh, Nate (November 15, 2018). "The AMD Radeon RX 590 Review, feat. XFX & PowerColor: Polaris Returns (Again)". anandtech.com. Archived from the original on November 15, 2018. Retrieved November 24, 2018.
  49. ↑ Kampman, Jeff (January 5, 2017). "The curtain comes up on AMD's Vega architecture". TechReport.com. Retrieved January 10, 2017.
  50. ↑ Shrout, Ryan (January 5, 2017). "AMD Vega GPU Architecture Preview: Redesigned Memory Architecture". PC Perspective. Retrieved January 10, 2017.
  51. ↑ Kampman, Jeff (October 26, 2017). "AMD's Ryzen 7 2700U and Ryzen 5 2500U APUs revealed". Techreport.com. Retrieved October 26, 2017.
  52. ↑ Raevenlord (March 1, 2017). "On NVIDIA's Tile-Based Rendering". techPowerUp.
  53. ↑ "Vega Teaser: Draw Stream Binning Rasterizer". Anandtech.com. January 5, 2017. Archived from the original on January 7, 2017.
  54. ↑ "Radeon RX Vega Revealed: AMD promises 4K gaming performance for $499 – Trusted Reviews". Trustedreviews.com. July 31, 2017. Archived from the original on July 14, 2017. Retrieved March 20, 2017.
  55. ↑ "The curtain comes up on AMD's Vega architecture". Techreport.com. Archived from the original on September 1, 2017. Retrieved March 20, 2017.
  56. ↑ Kampman, Jeff (January 23, 2018). "Radeon RX Vega primitive shaders will need API support". Techreport.com. Retrieved December 29, 2018.
  57. ↑ "ROCm-OpenCL-Runtime/libUtils.cpp at master · RadeonOpenCompute/ROCm-OpenCL-Runtime". github.com. May 3, 2017. Retrieved November 10, 2018.
  58. ↑ "The AMD Radeon RX Vega 64 & RX Vega 56 Review: Vega Burning Bright". Anandtech.com. August 14, 2017. Archived from the original on August 14, 2017. Retrieved November 16, 2017.
  59. ↑ "AMD's Vega Mobile Lives: Vega Pro 20 & 16 in Updated MacBook Pros In November". Anandtech.com. October 30, 2018. Archived from the original on October 31, 2018. Retrieved November 10, 2018.
  60. ↑ "AMD Announces Radeon Instinct MI60 & MI50 Accelerators: Powered By 7nm Vega". Anandtech.com. November 6, 2018. Archived from the original on November 7, 2018. Retrieved November 10, 2018.
  61. ↑ "AMD Unveils World's First 7nm Gaming GPU – Delivering Exceptional Performance and Incredible Experiences for Gamers, Creators and Enthusiasts" (Press release). Las Vegas, Nevada: AMD. January 9, 2019. Retrieved January 12, 2019.
  62. ↑ Ferreira, Bruno (May 16, 2017). "Ryzen Mobile APUs are coming to a laptop near you". Tech Report. Retrieved May 16, 2017.
  63. ↑ "AMD Unveils World's First 7nm Datacenter GPUs – Powering the Next Era of Artificial Intelligence, Cloud Computing and High Performance Computing (HPC) | AMD". AMD.com (Press release). November 6, 2018. Retrieved November 10, 2018.
  64. ↑ "RadeonFeature". x.Org. Retrieved November 21, 2022.
  65. ↑ "Radeon: Dissecting the Polaris Architecture" (PDF). Archived from the original (PDF) on December 19, 2020. Retrieved October 8, 2026.
  66. ↑ "AMD Tahiti GPU Specs". TechPowerUp. Retrieved November 20, 2022.
  67. ↑ "AMD Pitcairn GPU Specs". TechPowerUp. Retrieved November 20, 2022.
  68. ↑ "AMD Cape Verde GPU Specs". TechPowerUp. Retrieved November 20, 2022.
  69. ↑ "AMD Oland GPU Specs". TechPowerUp. Retrieved November 20, 2022.
  70. ↑ "AMD Hainan GPU Specs". TechPowerUp. Retrieved November 20, 2022.
  71. ↑ "AMD Bonaire GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  72. ↑ "AMD Hawaii GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  73. ↑ "AMD Topaz GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  74. ↑ "AMD Tonga GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  75. ↑ "AMD Fiji GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  76. ↑ "AMD Ellesmere GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  77. ↑ "AMD Baffin GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  78. ↑ "AMD Lexa GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  79. ↑ "AMD Polaris 22 GPU Specs". TechPowerUp. Retrieved February 13, 2026.
  80. ↑ "AMD Vega 10 GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  81. ↑ "AMD Vega 12 GPU Specs". TechPowerUp. Retrieved November 21, 2022.
  82. ↑ "AMD Vega 20 GPU Specs". TechPowerUp. Retrieved November 21, 2022.