PowerPC e300

A 400 MHz MPC5200 from an EFIKA computer.

The PowerPC e300 is a family of 32-bit PowerPC microprocessor cores developed by Freescale Semiconductor introduced in 2004. It was designed primarily for system-on-a-chip (SoC) designs with speed ranging up to 800 MHz, thus making them ideal for embedded applications. It was one of the first products released by Freescale, which had formed as a spin-off of Motorola in 2004.

The e300 is a superscalar RISC core with 16/16 or 32/32 kB L1 data/instruction caches, a four-stage pipeline with load/store, system register, branch prediction and integer unit with optional double-precision FPU. The e300 core is completely backwards compatible with the G2 and PowerPC 603e cores from which it derives.

The e300 core is the CPU part of several SoC processors from Freescale:

References

  1. ↑ Brown, Eric (May 13, 2009). "802.11n access point design taps new PowerQUICC chip". LinuxDevices. QuinStreet. Archived from the original on August 13, 2025.
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  3. ↑ Wright, Maury (May 23, 2012). "Designers Face Complex Choices as the Line between MCUs and Microprocessors Blurs". Electronic Products. AspenCore.
  4. ↑ Rochange, Christine; Pascal Sainrat; Sascha Uhrig (2014). Time-Predictable Architectures (ebook ed.). Wiley. ISBN 111879026X – via Google Books.
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  6. ↑ Hallinan, Christopher (2006). Embedded Linux Primer: A Practical Real-World Approach. Pearson Education. pp. 50–51. ISBN 9788131713525 – via Google Books.
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  8. ↑ Benz, Benjamin (March 2008). "Triple-Core für Ultra-Mobile-PCs" [Triple-Core for Ultra-Mobile-PCs]. c't (in German). Heinz Heise. p. 32 – via the Internet Archive.
  9. ↑ Frenzel, Louis E. (April 12, 2007). "High-Density SoC Makes GPON and FTTH Triple Play Practical and Affordable". Electronic Design. Vol. 55. Penton Media. p. 28. ProQuest 221008296.