SHA instruction set

A SHA instruction set is a set of extensions to the ARM, Power, RISC-V and x86 instruction set architecture which support hardware acceleration of the Secure Hash Algorithm (SHA) family.

ARM

SHA-1 and SHA-256 instructions appeared as optional features (FEAT_SHA1 and FEAT_SHA256) in the Arm V8.0 architecture introduced in 2011. The instructions are:

SHA-512 and SHA-3 instructions appeared as optional features (FEAT_SHA512 and FEAT_SHA3) in the Arm V8.2 architecture. The instructions are:

A scalable vector extension (SVE) version of the SHA-3 instructions appeared as an optional feature (FEAT_SVE_SHA3) in the Arm V9.0 architecture.

Power

Vector instructions for the Sigma functions for SHA-256 (vshasigmaw) and SHA-512 (vshasigmad) were added in the specification for Power ISA v.2.07 released in May 2013. The same instruction performs either Σ₀, Σ₁, σ₀ or σ₁ as described in the SHA-2 standard (FIPS-180-4) depending on parameters.

RISC-V

SHA2 instructions are part of the Zknh extension part of the RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions ratified in November 2021.

As SHA-512 is defined on 64-bit words, the instructions for SHA-512 differ in RV32 and RV64, with some RV32 instructions for SHA-512 split the elementary sigma operations in half in order to operate on a single 32-bit register.

The instructions are:

x86 architecture processors

The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256 and were specified in 2013 by Intel. Instructions for SHA-512 were introduced in Arrow Lake and Lunar Lake in 2024.

The newer SHA-512 instruction set comprises AVX-based versions of the original SHA instruction set marked with a V prefix and these three new AVX-based instructions for SHA-512:

AMD

All recent AMD processors support the original SHA instruction set:

Intel

The following Intel processors support the original SHA instruction set:

The following Intel processors support the newer SHA-512 instruction set:

References

  1. ↑ "The Armv8.0 architecture extension". Retrieved 2025-12-11.
  2. ↑ "The Armv8.2 architecture extension". Retrieved 2025-12-11.
  3. ↑ "The Armv9.0 architecture extension". Retrieved 2025-12-11.
  4. ↑ "Power ISA Version 2.07" (PDF). Power.org. 2013-05-15. Retrieved 2023-11-02.
  5. ↑ "Zknh - NIST Suite: Hash Function Instructions". Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1. RISC-V International. Retrieved 4 September 2026.
  6. ↑ "Ratified Extensions". Retrieved 2025-02-12.
  7. ↑ "New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors". intel.com. Retrieved 2024-07-25.
  8. ↑ "Zen - Microarchitectures - AMD - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
  9. ↑ "Goldmont - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
  10. ↑ "Cannon Lake - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
  11. ↑ "Ice Lake (client) - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25.